As shown in FIG. 13, in a conventional manufacturing process for an epitaxial layer, a distal end and a proximal end of a grown silicon single crystal ingot are cut off to provide a block shape, an outer diameter of the ingot is ground in order to uniform a diameter of the ingot so that a block body can be obtained, an orientation flat or an orientation notch is formed to this block body to indicate a specific crystal orientation, and then the block body is sliced with a predetermined angle with respect to a rod axis direction (a step 1). A wafer peripheral portion of the sliced wafer is chamfered to avoid a crack or a chip of the wafer peripheral portion (a step 2). Subsequently, double disk surface grinding (which will be referred to as DDSG hereinafter) that allows both front and rear surfaces of the silicon wafer to be ground is applied as a smoothing step (a step 3). Then, single disk surface grinding (which will be referred to as SDSG hereinafter) that allows the front surface alone of the wafer to be ground or allows the front and rear surfaces of the wafer to be ground one by one is carried out (a step 4). Subsequently, double disk surface polishing (which will be referred to as DSP hereinafter) that allows both the front and rear surfaces of the wafer to be simultaneously polished is effected (a step 5). Then, single disk surface polishing (which will be referred to as SMP hereinafter) that allows the front surface alone of the wafer to be polished or allows the front and rear surfaces of the wafer to be polished one by one is carried out (a step 6). Further, when an epitaxial layer made of a silicon single crystal is formed on the surface of the wafer by epitaxial growth (a step 7), a desired epitaxial wafer can be obtained.
However, the conventional manufacturing process has the following problem.
When machining processing, e.g., slicing or grinding is applied, a mechanical damage or a machining scratch is necessarily formed on the wafer. Since an epitaxial layer forming step based on epitaxial growth is a process that emphasizes a scratch or a damage (a distortion of a crystal lattice) present on the wafer surface, a crystal defect, e.g., a dislocation or a stacking fault occurs in the epitaxial layer with a defective part caused due to machining processing such as grinding as a starting point, and this defect is elicited as a surface defect on an epitaxial layer surface in some cases. Furthermore, when a scratch or a machining damage caused due to machining processing is serious, a slip may occur in the formed epitaxial layer. Moreover, since the number of steps to manufacture an epitaxial layer is large, a throughput is reduced and a cost is increased.
In order to solve this problem, there is disclosed a method for manufacturing a silicon epitaxial wafer characterized by performing a vapor growth step of growing a silicon single crystal thin film from vapor on a silicon single crystal substrate; a step of effecting water polishing; and a polishing step using an abrasive in the mentioned order (see, e.g., Patent Document 1). In this method disclosed in Patent Document 1, a silicon single crystal substrate before the vapor growth step is obtained as follows. First, a silicon single crystal ingot is cut into a block, subjected to external-diameter grinding, and then sliced. Subsequently, outer rims on both surfaces of the sliced silicon single crystal wafer are chamfered, and then both the surfaces are lapped by using a loose abrasive. The lapping wafer is immersed in an etchant to chemically etch both the surfaces, thereby obtaining a chemically etched wafer. This chemically etched wafer is determined as the silicon single crystal substrate, and a silicon single crystal thin film is grown from vapor on this substrate. In the method disclosed in Patent Document 1, occurrence of a scratch defect due to a protruding defect formed on the surface of the vapor-grown silicon single crystal thin film can be suppressed, and a height of this protruding defect can be reduced.
Patent Document 1: Japanese Examined Patent Application Publication No. 2002-43255 (claim 1, paragraphs and [0013] to [0015])